Transistor of semiconductor device, and method for manufacturing the same

ABSTRACT

A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an epitaxial source/drain junction layer having an insulating film thereunder. The method comprises the step of forming a under-cut under an epitaxial source/drain junction layer so that an insulating film filling the under-cut can be formed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to transistor of semiconductor device andmethod for manufacturing the same, and more particularly to improvedtransistor of memory device and method for manufacturing the same whichprovides a high speed and high integrated device by preventingdeterioration of the characteristics of the device resulting fromincrease of impurity concentration as the integration of the device isincreased.

2. Description of the Background Art

As the integration of a semiconductor device has been increased,integration of a DRAM has increased. However, the refresh time of theDRAM is almost double in each generation because of a high speed and lowpower requirements.

As the density of a memory device continuously increases, theconcentration of impurities implanted into a substrate must be increasedto minimize short channel effects, threshold voltages and leakagecurrents. However, the increase of the concentration of impuritiesresults in increase of junction electric intensity, which generatesshort channel effects and leakage currents.

Moreover, the increase of concentration increases junction capacitance,thereby reducing the operation speed of the device.

As described above, in the conventional transistor of the semiconductordevice and a method for manufacturing the same, the characteristics ofthe device is degradeddue to the increased concentration of impuritiesimplanted into the substrate, thereby making the achievement of the highoperation speed and high integration of the semiconductor device moredifficult.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide atransistor of a semiconductor device and a method for forming the samewherein capacitance generated by junction leakage current and junctiondepletion in a source/drain junction layer is remove to achieve a highspeed and high integration of the device.

According to one aspect of the present invention, a transistor of asemiconductor device, comprising: an epitaxial channel region disposedon an active region of a semiconductor substrate; a stacked structure ofan insulating film and an epitaxial source/drain junction layer disposedat both sides of the channel region; and a stacked structure of a gateinsulating film and a gate electrode disposed on the epitaxial channelregion, wherein at least a portion of the gate insulating film overlapwith the source/drain junction layer is provided.

According to another aspect of the invention, a method for forming atransistor of a semiconductor device., comprising the steps of: forminga stacked structure of a first epitaxial layer and a second epitaxiallayer on a semiconductor substrate; forming a device isolation film oftrench type defining an active region, wherein a thickness of the deviceisolation film is substantially the same as that of the stackedstructure; implanting an impurity into the second epitaxial layer usingthe device isolation film as a mask; sequentially forming a thermaloxide film and a sacrificial film on the entire surface of the resultingstructure; etching the sacrificial film, the thermal oxide film, and thesecond and first epitaxial layers using a gate electrode mask to form anopening exposing the semiconductor substrate; removing the firstepitaxial layer to form an under-cut under the second epitaxial layer;forming an insulating film filling the under-cut; growing a thirdepitaxial layer on the semiconductor substrate exposed by the opening;removing the sacrificial film and the thermal oxide film; implanting animpurity into the third epitaxial layer to form a channel region; andforming a gate electrode on the channel region is provided.

According to yet another aspect of the invention, a method for forming atransistor of a semiconductor device, comprising the steps of: forming astacked structure of a first epitaxial layer and a second epitaxiallayer on a semiconductor substrate; forming a device isolation film oftrench type defining an active region; forming a dummy gate electrode onthe second epitaxial layer; implanting an impurity into the secondepitaxial layer using the dummy gate electrode as a mask; forming aninsulating film spacer at a sidewall of the dummy gate; forming athermal oxide film on the entire surface of the resulting structure;forming a planarized interlayer insulating film exposing the top surfaceof the dummy gate; etching the dummy gate and the second and firstepitaxial layers therebelow to form an opening exposing thesemiconductor substrate; removing the first epitaxial layer to form anunder-cut under the second epitaxial layer; forming an insulating filmfilling the under-cut; growing a third epitaxial layer having animpurity implanted therein on the semiconductor substrate exposed by theopening; and forming a stacked structure of a gate oxide film and a gateelectrode on the third epitaxial layer is provided.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become better understood with reference tothe accompanying drawings which are given only by way of illustrationand thus are not limitative of the present invention, wherein:

FIG. 1 is a layout diagram illustrating an active region and a gateregion formed in one field;

FIGS. 2 a to 2 f are cross-sectional diagrams illustrating sequentialsteps of a method for forming a transistor of a semiconductor device inaccordance with a first embodiment of the present invention; and

FIGS. 3 a to 3 i are cross-sectional diagrams illustrating sequentialsteps of a method for forming a transistor of a semiconductor device inaccordance with a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A transistor of a semiconductor device and a method for forming the samein accordance with preferred embodiments of the present invention willnow be described in detail with reference to the accompanying drawings.

FIG. 1 is a layout diagram illustrating an active region and a gateelectrode region 22 formed on a semiconductor substrate 11, and FIGS. 2a to 2 f are cross-sectional diagrams illustrating sequential steps of amethod for forming a transistor of a semiconductor device in accordancewith a first embodiment of the present invention, taken along lines I-Iof FIG. 1.

Referring to FIG. 2 a, an first epitaxial layer 13 and a conductivesecond epitaxial layer 15 are sequentially formed on the semiconductorsubstrate 11 consisting of silicon.

Preferably, the first epitaxial layer 13 is an epitaxial SiGe layerformed under an atmosphere of a mixture gas of a gas from the groupconsisting of GeH₄, SiH₄, SiH₂Cl₂ and combinations thereof, HCl and H₂,and has a thickness ranging from 50 to 1000 Å, and the second epitaxiallayer 15 is an epitaxial Si layer formed under an atmosphere of a gasfrom the group consisting of SiH₄, SiH₂Cl₂ and combinations thereof, HCland H₂, and has a thickness ranging from 50 to 1000 Å.

A pad oxide film (not shown) and a nitride film (not shown) aresequentially formed on the entire surface of the resulting structure.

Thereafter, the nitride film, the oxide film, the second epitaxial layer15, the first epitaxial layer 13 and a predetermined depth ofsemiconductor substrate 11 are etched via a photoetching process using adevice isolation mask (not shown) to form a trench. A device isolationfilm 17 is formed by filling the trench to define an active region.

Next, the second epitaxial layer 15 is subjected to an implant processusing the device isolation film 17 as a mask. The implant process ispreferably performed using As having a concentration ranging from 1.0E12 to 5.0 E13 atoms/cm² with an energy ranging from 10 to 100 KeV.Other conventional impurities may be used.

A thermal oxide film 19 is formed on the entire surface of the resultingstructure. The thermal oxide film preferably has a thickness rangingfrom 10 to 200 Å. A sacrificial film 21 is then formed on the thermaloxide film 19. Preferably, the sacrificial film 21 may be an oxide film,nitride film or polysilicon film having a thickness ranging from 500 to3000 Å and used as a mask.

Referring to FIG. 2 b, a gate electrode region 22 exposing thesemiconductor substrate 11 is formed by sequentially etching thesacrificial film 21, the thermal oxide film 19, the second epitaxiallayer 15 and the first epitaxial layer 13 via a photoetching processusing a mask exposing an region corresponding to the gate electroderegion 22 of FIG. 1.

Referring to FIG. 2 c, the first epitaxial layer 13 exposed by a lowersidewall of the gate electrode region 22 is removed to form an under-cut23 under the second epitaxial layer 15. Preferably, the process forremoving the exposed portion of the first epitaxial layer 13 is a wetetching process or an isotropic dry etching process utilizing etchingselectivity differences among adjacent layers and the first epitaxiallayer 13.

Specifically, the wet etching process is preferably performed using asolution containing H₂O, H₂O₂ and NH₄OH having a ratio of 5:1:1 at atemperature ranging from 70 to 80° C. (ref. F. S. Johnson et al. journalof electronic materials, vol 21, p. 805-810, 1992). The isotropic dryetching process is preferably a plasma etching process using HBr, O₂ andCl₂, and more preferably performed using microwaves to improve isotropicetching properties. In addition, the plasma etching process may beperformed using SF₆.

Now referring to FIG. 2 d, an insulating film 25 for filling theunder-cut 23 is formed on the entire surface of the resulting structure.Preferably, the insulating film 25 is an oxide film or nitride film.

The insulating film 25 is preferably formed via thermal oxidation,chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Preferably, the CVD process is performed using SiH₄ and N₂O under apressure of 50 Torr and at a temperature ranging from 50 to 800° C. Thethermal oxidation process is a dry or wet process performed at atemperature of 700 to 1100° C.

Referring to FIG. 2 e, a wet etching process is performed so that onlythe portion of the insulating film 25 in the under-cut 23 remains. Thewet etching process is preferably performed using a HF group etchingsolution.

As shown in FIG. 2 f, a third epitaxial layer 27 is grown on thesemiconductor substrate 11 exposed by the gate electrode region 22.

Preferably, the third epitaxial layer 27 is an epitaxial Si layer havinga thickness ranging from 100 to 2000 Å formed under an atmosphere of amixture gas of a gas from the group consisting of SiH₄, SiH₂Cl₂ andcombinations thereof, HCl and H₂.

The sacrificial oxide film 21 and the thermal oxide film 19 are removedvia a wet etching process. Preferably, the wet etching process isperformed by utilizing the etching selectivity difference among adjacentother layers and the sacrificial oxide film 21.

A channel region is formed on the third epitaxial layer 27 by performinga channel implant process and a punch stop implant process.

A gate electrode having a stacked structure of a gate oxide film 29, aconductive layer for gate electrode 31 and a hard mask layer 33 isformed via a photoetching process using a gate electrode mask.Conventional conductive materials may be used as the conductive layerfor gate electrode 31. The hard mask layer 33 is preferably a nitridefilm or an oxide film.

The formation of the channel region and removal of the sacrificial oxidefilm 21 and the thermal oxide film 19 may be performed prior to theformation of the gate electrode.

In the transistor of the semiconductor device formed according to themethod of FIGS. 2 a to 2 f, the conductive third epitaxial layer 27formed in the active region of the semiconductor substrate 11corresponds to the channel region of the transistor. The stackedstructure of the insulating film 25 and the conductive second epitaxiallayer 15 is formed at both sides of the third epitaxial layer 27, andthe gate insulating film 29 and the gate electrode 31 are formed on thethird epitaxial layer 27. The second epitaxial layer 15 corresponds to asource/drain junction layer, and at least a portion of the gateinsulating film 29 overlap with the second epitaxial layer 15.

FIGS. 3 a to 3 i are cross-sectional diagrams illustrating sequentialsteps of a method for forming a transistor of a semiconductor device inaccordance with a second embodiment of the present invention, takenalong lines I-I of FIG. 1.

Referring to FIG. 3 a, an first epitaxial layer 43 and a conductivesecond epitaxial layer 45 are sequentially formed on the semiconductorsubstrate 41 comprised of silicon. Preferably, the first epitaxial layer43 is an epitaxial SiGe layer having a thickness ranging from 50 to 1000Å formed under an atmosphere of a mixture gas of a gas from the groupconsisting of GeH₄, SiH₄, SiH₂Cl₂ and combinations thereof, HCl and H₂,and the second epitaxial layer. 45 is an epitaxial Si layer having athickness ranging from 50 to 1000 Å formed under an atmosphere of amixture gas of a gas from the group consisting of SiH₄, SiH₂Cl₂ andcombinations thereof, HCl and H₂.

A pad oxide film (not shown) and a nitride film (not shown) aresequentially formed on the entire surface of the resulting structure.

Thereafter, the nitride film, the oxide film, the second epitaxial layer45, the first epitaxial layer 43 and a predetermined depth ofsemiconductor substrate 41 are etched via a photoetching process using adevice isolation mask (not shown) to form a trench. A device isolationfilm 47 is formed by filling the trench to define an active region.

Referring to FIG. 3 b, a polysilicon layer (not shown) is formed on theentire surface of the resulting structure., and then etched via aphotoetching process using a gate electrode mask to form a dummy gateelectrode 49 in a predetermined region where a gate electrode region isto be formed. The thickness of the polysilicon layer is substantiallythe same as that of the gate electrode formed in a subsequent process,for example, 500 to 3000 Å in thickness. An oxide film or nitride filmmay be used other than the polysilicon layer.

Thereafter, the second epitaxial layer 45 is subjected to an implantprocess using the dummy gate electrode 49 as a mask. The implant processis preferably performed using As having a concentration ranging from 1.0E12 to 5.0 E13 atoms/cm² with an energy ranging from 10 to 100 KeV.Other conventional impurities may be used.

The implant process may also be performed prior to the formation of thepolysilicon layer using the device isolation film 47 as a mask.

Referring to FIG. 3 c, an insulating film spacer 51, preferably anitride film or an oxide film is formed at sidewalls of the dummy gateelectrode 49. A thermal oxide film 53 is then formed on the entiresurface of the resulting structure.

Now referring to FIG. 3 d, an interlayer insulating film 55 is formed onthe entire surface of the resulting structure, and then planarized toexpose the top surface of the dummy gate electrode 49. Preferably, theplanarization process is a CMP process.

Referring to FIG. 3 e, the exposed dummy gate electrode 49 is firstremoved, and the second epitaxial layer 45 and the first epitaxial layer43 are etched using the interlayer insulating film 55 and the insulatingfilm spacer 51 as a mask to form a gate electrode region 57 exposing thesemiconductor substrate 41.

Referring to FIG. 3 f, the first epitaxial layer 43 exposed by a lowersidewall of the gate electrode region 57 is removed to form an under-cut59 under the second epitaxial layer 45. Preferably, the process forremoving the exposed portion of the first epitaxial layer 43 is a wetetching process or an isotropic dry etching process utilizing etchingselectivity differences among adjacent and the first signal-crystallinelayer 43.

Specifically, the wet etching process is preferably performed using asolution containing H₂O, H₂O₂, NH₄OH having a ratio of 5:1:1 at atemperature ranging from 70 to 80° C. (ref. F. S. Johnson et al. journalof electronic materials, vol 21, p. 805-810, 1992). The isotropic dryetching process is preferably a plasma etching process using HBr, O₂ andCl₂, and more preferably performed using microwaves to improve isotropicetching properties. In addition, the plasma etching process may beperformed using SF₆.

Referring to FIG. 3 g, an insulating film 61 for filling the under-cut59 is formed on the entire surface of the resulting structure.Preferably, the insulating film 61 is an oxide film or a nitride film.

The insulating film 61 is preferably formed via thermal oxidation,chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Preferably, the CVD process is performed using SiH₄ and N₂O under apressure of 50 Torr and at a temperature ranging from 50 to 800° C. Thethermal oxidation process is a dry or wet process performed at atemperature ranging from 700 to 1100° C.

Referring to FIG. 3 h, a wet etching process is performed so that onlythe portion of the insulating film 61 in the under-cut 59 remains. Thewet etching process is preferably performed using a HF group etchingsolution.

Referring to FIG. 3 i, a third epitaxial layer 63, which is preferablyan epitaxial Si layer having a thickness ranging from 100 to 2000 Å, isgrown on the semiconductor substrate 41 exposed by the gate electroderegion 57.

A channel region is formed on the third epitaxial layer 63 by performinga channel implant process and a punch stop implant process.

A gate oxide film 65 is grown on the third epitaxial layer 63, and aconductive layer for gate electrode 67 is formed on the gate oxide film65, and then planarized using the interlayer insulating film 55 as anetch barrier to form a gate electrode.

The gate electrode may include a stacked structure of a conductive layerand a hard mask layer.

As discussed earlier, in accordance with the present invention, thetransistor of the semiconductor device and the method for forming thesame have the following advantages:

1. Generation of junction leakage current is prevented.

2. Removal of capacitance generated by junction depletion providesimproved operation speed of the device.

3. Improved short channel effects/drain induced barrier loweringcharacteristics due to the decrease in junction depth provide decreaseof a critical dimension of the gate electrode and less threshold voltagereduction.

4. The epitaxial Si layer consisting the source/drain junction regionrepresses depletion in a bulk-wise direction to improve punch-throughcharacteristics and allows a reduction of the dose of punch stop implantto improve refresh characteristics of the DRAM.

5. The improved punch-through characteristics allow reduction of channelthreshold voltage control implant dose, thereby improving swingphenomenon and leakage current characteristics in an off state.

6. An increase in junction breakdown voltage allows a high-speedoperation of the device which uses a high driving voltage.

7. A remarkable decrease in leakage current between the devices allowsreduction of the depth and width of the device isolation film andachievement of high integration.

8. The epitaxial channel region and the source/drain junction regionprovide an improved interface characteristics of the semiconductorsubstrate.

As the present invention may be embodied in several forms withoutdeparting from the spirit or essential characteristics thereof, itshould also be understood that the above-described embodiments are notlimited by any of the details of the foregoing description, unlessotherwise specified, but rather should be construed broadly within itsspirit and scope as defined in the appended claims, and therefore allchanges and modifications that fall within the metes and bounds of theclaims, or equivalences of such metes and bounds are therefore intendedto be embraced by the appended claims.

1. A transistor of a semiconductor device, comprising: an epitaxialchannel region disposed on an active region of a semiconductorsubstrate; a stacked structure of an insulating film and an epitaxialsource/drain junction layer disposed at both sides of the channelregion; and a stacked structure of a gate insulating film and a gateelectrode disposed on the epitaxial channel region, wherein at least aportion of the gate insulating film overlap with the source/drainjunction layer.
 2. The transistor of claim 1, wherein the insulatingfilm is an oxide film or a nitride film.
 3. The transistor of claim 1,wherein the insulating film and the source/drain junction layer have athickness ranging from 50 to 1000 Å, respectively.
 4. The transistor ofclaim 1, further comprising a device isolation film defining the activeregion, the thickness of the device isolation film being substantiallythe same as that of the stacked structure of the insulating film and thesource/drain junction layer.
 5. The transistor of claim 1, wherein thesource/drain junction layer and the channel region consist of epitaxialSi layers.
 6. The transistor of claim 1, wherein the thickness of theepitaxial channel region is substantially the same as that of thestacked structure of the insulating film and the source/drain junctionlayer. 7-26. (canceled).